The present invention relates to a semiconductor memory device, and more particularly to a semiconductor memory device which can be operated at high speed by the increase of the current in a bit line.
Common semiconductor memory devices include a RAM(Random Access Memory) which can perform both a writing operation and a reading operation, and a ROM(Read Only Memory) which can perform only a reading operation. A RAM may be a DRAM(dynamic RAM) or a SRAM(static RAM), while a ROM may be a mask ROM or a programmable ROM.
A memory device includes a plurality of memory cells arranged in a matrix, where each memory cell corresponds to at least one word line and at least one bit line. A word line is applied with a signal which controls the access to the corresponding cells. If the word line is active, access should be allowed to the corresponding cells, otherwise, it shouldn't be allowed. Data is transferred to or from a memory cell through a bit line.
The detection of data in a memory device usually employs NAND logic circuitry or NOR logic circuitry. A power supply node is coupled to the bit line through a load and the other end of the bit line is coupled to a sense amplifier. In a memory device employing NAND circuitry, a plurality of memory cells constitutes a string and a plurality of strings may be coupled to one bit line in order to increase the density of integration. As the number of strings coupled to one bit line increases, both the stray capacitance of the bit line and the junction capacitance which exists between the bit line and the string are increased. This results in increased total bit line capacitance which reduces bit line current and operation speed.